A Novel Digital Adder Design Based on Residue Number System with Special Set of Moduli

As one of the processor's ALU performance issues, the carry propagation during the addition operation limits the speed of arithmetic operation. This work aims to build an Efficient Hardware Design for an Adder based on Residual Numbering System (RNS), with a pre-specified special set of moduli to simplify the implementation for the purpose of proving the feasibility of its usage. Our design can be divided into three basic components: two conversion modules, and an addition module. The conversion modules here are based on a special set of moduli numbers to simplify the hardware implementation. In this work, we focus on forward conversion (conventional to RNS) leaving reverse converter {RNS to conventional} for future works. Depending on this notion, we implemented each component individually in VHDL and then to assemble these components with each other to build a whole RNS-Adder. Simulation results are very attractive in terms of critical path delay.